The 60 GHz unlicensed band with his wide channels and relatively high power emission has raised great interest in these years. Various and interesting applications have been proposed and a lot of investments have been delivered to give the opportunity to open this new market at the ultra-wideband applications. The principal areas of application are oriented to mass production as the wireless high definition video and ultra wideband personal area network (WPAN). Others very interesting applications for this technology are the wireless sensor networks (WSN). A very interesting field of application for the WSN is the structure health monitoring (structures could be planes, cars, engines or human body as well).  Many sensors (tens or hundreds, depending on the data rate acquisition) can be placed in the device under test and, thanks to the available UWB channels they allow the acquisition of an enormous number of data. To increase the attractiveness and to favorite an environment of application as wider as possible, cheaper CMOS bulk technology is adopted: the silicon technology permits a mass production of component at very low cost. Applications like WSNs (with battery drive cells) require a very low power consumption to increase the tags'  lifetime, therefore an energy efficient transceiver and power saving systems must be designed to assure this request. This thesis work is focused on the design of the 60 GHz RF transceiver.  As previously said, the CMOS technology is adopted to reduce the production cost and, consequently, the final price of the system. Considering that, the project is oriented to the creation of a WSN for structure health monitoring, battery driven systems are required. Therefore, the design specifications are principally oriented to the power consumption reduction in order to maintain a high signal gain and a bandwidth as wider as possible around the 60 GHz central frequency. To satisfy these constraints the research needs to be addressed towards two different ways. As for the active blocks (mixers, amplifiers, voltage controlled oscillators and buffer) the analysis of low power architecture is mandatory. More in detail novel architectural solutions must be proposed, or the power optimization of already used structures must be investigated. As for the passive blocks (power splitters, baluns, couplers, lines and antennas) the minimization of the insertion loss is the target to reach. This goal can be attained following the same strategy adopted for the active blocks: novel architecture proposition or existing devices improvement are requested to raise the performance of the transceiver maintaining low power consumption.