Ultra-low-power logic gates based on capacitive based on MEMS devices operating in adiabatic regime
Logic gates are devices that act as building blocks for digital circuits. Based on the combination of digital signals coming from their inputs, logic gates perform logical functions based on Boolean algebra that are fundamental to digital circuits. In modern practice, most gates, e.g. in microprocessors, are made from MOSFETs (metal–oxide–semiconductor field-effect transistors) .
In the sixties in the last century Rolf Landauer has proposed the principle describing the smallest amount of energy that is used to switch between two logic states – “0” and “1”, that is, to erase one bit of information. This principle is now known as the Landauer’s limit and claims that the energy requirement, at room temperature for one operation, should be of the order of magnitude of zepto (10-21) joules. However, this limit is still far from being reached. The state-of-the-art MOSFET transistors dissipate ~1000 kBT even in advanced CMOS nodes during a single logic operation and therefore remain orders of magnitude above Landauer’s limit . The energy dissipation of digital circuits has been widely studied and can be explained by three different aspects:
- Dynamic losses, which occur during abrupt switching between two logic states,
- Static losses which are due to the non-zero leakage currents when the switch is “off”,
- In order to be able to distinguish two different states their energetic difference has to be well above the thermal noise level (kBT), which in turn increases the dynamic losses.
In our work, we aim to eliminate static and dynamic losses from logic circuits and therefore approach zero power dissipation during the logic operations. Lower dissipations however come at a cost of lower processing speed as this approach requires operating at low frequencies (speed limit comes from the device’s time constant). Some previous works in the field have made use of N/MEMS relays to pursue this goal [3-6]. Here, we propose capacitive (contactless – to overcome the issue of N/MEMS relays) MEMS devices based on comb-drive actuators for storing and transmission of the logic information in a differential architecture.
This work is performed in the framework of the ANR project ZerÔuate, involving 4 laboratories: CEA-LETI, LAAS, ESYCOM and G2ELAB.
 H. Fanet, Ultra Low Power Electronics and Adiabatic Solutions. Hoboken, NJ, USA: Wiley, 2016, doi: 10.1002/9781119006541
 R. Landauer, “Irreversibility and heat generation in the computing process,” IBM J. Res. Dev., vol. 5, no. 3, pp. 183–191, Jul. 1961, doi: 10. 1147/rd.53.0183
 H. Samaali, Y. Perrin, A. Galisultanov, H. Fanet, G. Pillonnet, et P. Basset, « MEMS four-terminal variable capacitor for low power capacitive adiabatic logic with high logic state differentiation », Nano Energy, vol. 55, p. 277-287, janv. 2019, doi: 10.1016/j.nanoen.2018.10.059.
 Z. A. Ye et al., “Demonstration of 50-mV digital integrated circuits with microelectromechanical relays,” in IEDM Tech. Dig., Dec. 2018, pp. 411–414, doi: 10.1109/IEDM.2018.8614663.
 G. Pillonnet, H. Fanet and S. Houri, "Adiabatic capacitive logic: A paradigm for low-power logic," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050996.
 Y. Perrin, A. Galisultanov, L. Hutin, P. Basset, H. Fanet and G. Pillonnet, "Contact-Free MEMS Devices for Reliable and Low-Power Logic Operations," in IEEE Transactions on Electron Devices, vol. 68, no. 6, pp. 2938-2943, June 2021, doi: 10.1109/TED.2021.3070844.
 P. Teichmann, “Adiabatic Logic: Future Trend and System Level Perspective,” Springer, 2012, DOI. 10.1007/978-94-007-2345-0.
- CEA-LETI in Grenoble (Contact G.Pillonnet, H.Fanet)
- LAAS-CNRS (Contact B.Legrand)
- ESYCOM in Paris (Contact P.Basset, A.Karami, F.Marty)
- G2ELAB in Grenoble (Contact O.Gallot, F.Aitken)