Retour au site du LAAS-CNRS

Abstract

A low phase noise and wide-bandwidth frequency divider has been developed in a 0.25 ¼m SiGe:C process. This paper discusses the BiCMOS design improvements used for ultra low phase noise applications like on-chip phase-noise measurement circuit. From a singleended signal provided by a local oscillator LO, the widebandwidth frequency divider circuit generates accurate quadrature signals. For the full 1kHz-5.5 GHz input frequency range, the frequency divider achieves an output quadrature error less than ±1°. This paper presents a novel architecture designed for improving phase noise and exhibits a measured residual phase noise of -164 dBc/Hz @ 100 kHz with a 3.5 GHz input frequency.

Mots-Clés / Keywords

Abstract

The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and onchip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 ¼m design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This operational amplifier provides both low noise and high gain performances. This operational amplifier has an area of only 660×250 ¼m2 with an equivalent input noise floor of only 1.1 nV/Hz square root at 10 kHz. The measured noise characteristics (versus total power consumption) are better than those of most operational amplifiers commonly adopted in low-frequency noise measurements. The AC gain is 83 dB and the unity gain bandwidth is 210 MHz, with a total current consumption of 18 mA at 2.5 V supply voltage.

Abstract

A test set-up for the characterization of microwave BAW resonators driven into nonlinear regime is presented. In this set-up, a network analyser is coupled to a spectrum analyser, in order to measure simultaneously the resonant frequencies and the nonlinear behaviour (harmonic generation). A power amplifier (5 W) is used at the network analyser output, because this nonlinear behaviour can only be observed at high power. Finally, the set-up is used to evaluate these properties on a set of SMR resonators.

Mots-Clés / Keywords

Abstract

A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This letter discusses the BiCMOS design improvements used for the phase accumulator and the phase-to-amplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 $mu$m technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm$^2$.

Mots-Clés / Keywords

Résumé

Cette présentation traite de la simulation en bruit de récepteurs homodynes, ou de discriminateurs de fréquence. Cette simulation est rendue difficile par la non prise en compte, par de nombreux simulateurs, du bruit au voisinage de la fréquence nulle. Notre approche utilise le simulateur Eldo-RF, et a été testée aussi bien pour la détection de phase (ou la mesure de bruit de phase résiduel) que pour la mesure de fréquence (mesure d'oscillateurs). Elle ouvre la voie vers l'optimisation de ces dispositifs.