150documents trouvés
A CMOS low loss / high linearity passive mixer for 2.45 GHz low power applications
M.CAMUS, B.BUTAYE, C.VIALLON, L.GARCIA, T.PARRA
ST Microelectronics, MOST, ST Ericsson
Manifestation avec acte : Asia Pacific Microwave Conference ( APMC ) 2012 du 04 décembre au 07 décembre 2012, Kaohsiung (Taiwan), Décembre 2012, 3p. , N° 12784
Lien : http://hal.archives-ouvertes.fr/hal-00783042
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Abstract
A fully integrated passive mixer suitable for 2.45 GHz low consumption and low cost applications is proposed and demonstrated in a 90 nm CMOS technology. An original operating principle is adopted which is based on the use of a local oscillator square signal exhibiting a duty cycle less than 1/4. By using such a LO driving, the mixer operates as a sampler and can theoretically achieve a voltage conversion gain of 0 dB. This mixer has been integrated in a complete monolithic receiver. According to simulations, measurements demonstrate improvements of 5 dB on gain and 3 dB on noise figure without any linearity degradation and any additional cost, when compared to a common LO driving of 1/2 duty cycle.
Solenoidal transformers for magnetic materials integration
L.OURAK, A.GHANNAM, D.BOURRIER, C.VIALLON, T.PARRA
MOST, TEAM
Manifestation avec acte : Asia Pacific Microwave Conference ( APMC ) 2012 du 04 décembre au 07 décembre 2012, Kaohsiung (Taiwan), Décembre 2012, 3p. , N° 12785
Lien : http://hal.archives-ouvertes.fr/hal-00783047
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This paper presents the design, fabrication and characterization of suspended solenoidal transformers fabricated using a low cost single step 3D copper electroplating process. The design and optimization of solenoidal transformers with and without magnetic core are performed using HFSS. After optimization, the suspended structures reveal good electrical performance. The addition of a magnetic core to these structures shows a significant improvement of its electrical properties. Thus, an increase of 10% on Gmax, 20% on coupling coefficient k, 80% on the quality factor Q and 350% on the inductance is observed. Under probe measurements carried on the suspended structures without magnetic core exhibit a Gmax of -1.45 dB and a Q of 28.5 at 2.5 GHz. The enhanced performance coupled with the low cost 3D process makes these transformers excellent candidates for today s RF applications.
Low cost 3D multilevel interconnect integration for RF and microwave applications
A.GHANNAM, L.OURAK, D.BOURRIER, C.VIALLON, T.PARRA
MOST, TEAM
Manifestation avec acte : Electronic Components and Technology Conference (ECTC 2012), San Diego (USA), 29 Mai - 1 Juin 2012, 5p. , N° 12440
Lien : http://hal.archives-ouvertes.fr/hal-00720570
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This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process.
Efficient low cost process for single step metal forming of 3D interconnected above-IC inductors
A.GHANNAM, L.OURAK, D.BOURRIER, C.VIALLON, T.PARRA
MOST, TEAM
Manifestation avec acte : European Solid-State Device Research Conference (ESSDERC 2011), Helsinki (Finlande), 12-16 Septembre 2011, 4p. , N° 11522
Lien : http://hal.archives-ouvertes.fr/hal-00627894/fr/
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This paper presents a novel and efficient low cost process capable of integrating high-Q above-IC inductors and their interconnects using a single electroplating step. It relies on the SU8 and BPN resist as well as an optimized electroplating technique to form the 3D interconnected inductor. The SU8 is used to form a thick layer located underneath the inductor to elevate it from the substrate. Then, the BPN is used as a high resolution mold (16:1) for copper electroplating. Standard or time optimized electroplating is later used to grow copper in a 3D manner, making the transition between all metallic layers straight forward. High-Q (55 @ 5 GHz) power inductors have been designed and integrated above an RF power LDMOS device using this process. Finally, the process capabilities are demonstrated by integrating a solenoid inductor using only two lithography masks and a single electroplating step.
Conception et optimisation de transformateurs solénoïdaux et toroïdaux pour l'intégration de matériaux magnétiques
L.OURAK, A.GHANNAM, C.VIALLON, T.PARRA
MOST
Manifestation avec acte : Journées Nationales Microondes (JNM 2011), Brest (France), 18-20 Mai 2011, 4p. , N° 11278
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124715Conception et caractérisation d'un mélangeur résistif en bande E réalisé en technologie BiCMOS SiGe0.13 um
M.MENEGHIN, T.EPERT, L.BARY, C.VIALLON, T.PARRA
MOST, 2I
Manifestation avec acte : Journées Nationales Microondes (JNM 2011), Brest (France), 18-20 Mai 2011, 4p. , N° 11356
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124916Conception et intégration " Above-IC " d'inductances à fort coefficient de surtension pour applications de puissance RF
A.GHANNAM, D.BOURRIER, C.VIALLON, J.M.BOULAY, G.BOUISSE, T.PARRA
MOST, TEAM, FREESCALE
Manifestation avec acte : Journées Nationales Microondes (JNM 2011), Brest (France), 18-20 Mai 2011, 4p. , N° 11223
Lien : http://hal.archives-ouvertes.fr/hal-00591689/fr/
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Résumé
Ce papier décrit l'optimisation du coefficient de surtension Q d'inductances intégrées au-dessus de substrats à très faibles résistivités (ρ < 0,1 Ω.cm). L'impact de ces résistivités sur les performances ainsi que l'inefficacité des plans de masses structurés sont présentés. Après optimisation du plan de masse, de l'épaisseur du diélectrique ainsi que des sections des métallisations, un coefficient de surtension de 58 à 5 GHz pour une valeur d'inductance totale de 0.8 nH est atteint. Un procédé technologique faible coût a été développé permettant l'intégration de ces inductances au-dessus de transistors LDMOS de puissance en utilisant la résine SU8 comme diélectrique.
Low Cost SU8 Based Above IC Process for High-Q RF Power Inductors Integration
A.GHANNAM, D.BOURRIER, C.VIALLON, T.PARRA
MOST, TEAM
Manifestation avec acte : Mediterranean Conference on Innovative Materials and Applications - CIMA 2011, Beyrouth (Liban), 15-17 Mars 2011, 4p. , N° 11224
Lien : http://hal.archives-ouvertes.fr/hal-00591690/fr/
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This paper presents a new process for integration of high-Q RF power inductors above low resistivity silicon substrates. The process uses the SU8 resin as a dielectric layer. The aim of using the SU8 is to form thick dielectric layer that can enhance the performance of the inductors. The flexibility of the process enables the possibility to realize complex shaped planar inductors with various dielectric and metal thicknesses to meet the requirements of the application. Q values of 55 at 5GHz has been demonstrated for an inductance value of 0.8nH using a 60 µm thick SU8 layer and 30 µm thick copper ribbons.
High-Q SU8 based above-IC inductors for RF power devices
A.GHANNAM, D.BOURRIER, C.VIALLON, J.M.BOULAY, G.BOUISSE, T.PARRA
MOST, TEAM, FREESCALE
Manifestation avec acte : Topical Mzeeting on Silicon Monolithic Integrated Circuits in RF Systems (SIRF 2011), Phoenix (USA), 16-19 Janvier 2011, pp.25-28 , N° 11005
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123795Conception et réalisation d'un dispositif d'extraction des paramètres électromagnétiques de matériaux dielectriques pour applications RF et micro-ondes
L.OURAK, D.SERON, C.VIALLON, T.PARRA
MOST
Manifestation avec acte : Journées de Caractérisation Microondes et Matériaux (JCMM 2010), Brest (France), 31 Mars - 2 avril 2010, 4p. , N° 10867
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