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Abstract

This paper proposes a 1D-analytical description of the injection ratio of a self-biased bipolar transistor under very high current injection conditions. Starting from an expression of the current gain based on the stored charge into the emitter and base regions, we derive a new analytical expression of the current injection ratio. This analytical description demonstrates the presence of an asymptotic limit for the injection ratio at very high current densities, as the ratio of electron/hole mobilities in the case of an NPN transistor and to the ratio of hole/electron saturation velocities for a PNP. Moreover, for the first time, a base narrowing effect is demonstrated and explained in the case of a self-biased PNP, in contrast with the base widening effect (Kirk effect [Kirk CT, A theory of transistor cutoff frequency (fT) falloff at high current densities, IRE Trans Electr Dev 1961: p. 16473]) reported for lower current density. These results are validated by numerical simulation and show a good agreement with experimental characterizations of transistors especially designed to operate under extreme condition such as electrostatic discharge (ESD) events

Abstract

This paper reports on the investigation of failure mechanisms of AlN-based capacitive RF MEMS switches. Electrostatic Discharge (ESD) experiments have been carried out by means of a Transmission Line Pulsing (TLP) technique. It has been observed that ESD stresses create some electric arcs and the degradations have been observed and analyzed. Microwave measurements have shown that ESD stress impacts the quality of the capacitive contact.

Abstract

This paper reports on the investigation of failure mechanisms of AlN-based capacitive RF MEMS switches. Electrostatic Discharge (ESD) experiments have been carried out by means of a Transmission Line Pulsing (TLP) technique. It has been observed that ESD stresses create some electric arcs and the degradations have been observed and analyzed. Microwave measurements have shown that ESD stress impacts the quality of the capacitive contact.

Abstract

This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A Very Fast Transmission Line Pulsing (VF-TLP) tester is used to inject a disturbance into an IC under operation. A system failure criterion is chosen and a critical stress level is extracted. A modeling methodology is also developed to precisely describe each part of the set up and provide a complete model that describes the IC response to ESD indirect effects.

Abstract

A new device dedicated to the ESD protection of high voltage I/Os is presented. In addition to the use of specific design guidelines, the concept consists in coupling an open-base lateral PNP with a vertical avalanche diode within the same structure to obtain a non-snapback behavior together with very good RON capabilities (~1©). The protection of high voltage I/Os with a narrow ESD design window ranging from 80V to 100V can be implemented in a reduced surface of 151*140 ¼m2, which represents a state-of-the-art breakthrough.

Mots-Clés / Keywords

Abstract

This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a Very Fast Transmission Line Pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full custom 0.18 ¼m CMOS IC.