133documents trouvés
Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD Propagation
N.MONNEREAU, F.CAIGNET, D.TREMOUILLES, N.NOLHIER, M.BAFLEUR
ISGE, ESE
Papier invité dans une revue : Microelectronics Reliability, 8p., Décembre 2012, http://dx.doi.org/10.1016/j.microrel.2012.04.012 , N° 10099
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128684Proof of concept of energy harvesting from aero acoustic noise
R.MONTHEARD, S.CARBONNE, M.BAFLEUR, V.BOITIER, J.M.DILHAC, X.DOLLAT, N.NOLHIER, E.PIOT, C.AIRIAU
ESE, Airbus SAS, 2I, I2C, ONERA, IMFT
Manifestation avec acte : International Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications ( PowerMEMS ) 2012 du 02 décembre au 05 décembre 2012, Atlanta (USA), Décembre 2012, 4p. , N° 12610
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128952Investingating the probability of susceptibility failure within ESD system level consideration
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Revue Scientifique : IEEE Transactions on Device and Materials Reliability, Vol.12, N°4, pp.599-606, Décembre 2012, DOI 10.1109/TDMR.2012.2218605 , N° 11058
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Abstract
Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.
Evidence of impurity impact ionization avalanche in p_type diamond
V.MORTET, A.SOLTANI, N.NOLHIER
MPN, IEMN, ESE
Manifestation sans acte : Workshop on Compound Semiconductor Devices and Integrated Circuits and Expert Evaluation & Control of Compound Semiconductor Materials and Technologies (WOCSDICE-EXMATEC 2012), Porquerolles (France), 30 Mai - 1 Juin 2012, 2p. , N° 12306
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127501Behavioral ESD protection modeling to perform system level ESD efficient design
F.CAIGNET, N.MONNEREAU, N.NOLHIER, M.BAFLEUR
ISGE, ESE
Conférence invitée : Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC 2012), Singapour (Singapour), 21-24 Mai 2012, pp.401-404 , N° 12442
Lien : http://hal.archives-ouvertes.fr/hal-00722644
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Abstract
For both Equipment Manufacturers (EM) and semiconductor suppliers, the prediction of ElectroStatic Discharge (ESD) events into design phase is becoming a challenging issue to insure rehability into system level considerations. This is mainly due to the shrinking of Integrated Circuits (IC) technology, which decreases the robustness level and increase the probability of failures. In this paper, we will present how to build IC's models taking into account behavioral description of ESD protections, to perform system level ESD simulations. The IBIS (Input/output Buffer Information Specification) models are mixed with information extracted from Transmission Line Pulsing (TLP) measurement's techniques to build system simulations. The methodology is detailed and proved in some case studies addressing the current propagation path and the susceptibility of the ICs. The main goal of the proposed model is that it could be shared by IC suppliers and EMs to ensure that ICs can handle system level ESD events.
Reliability assessment of electrostatically driven MEMS devices: based on a pulse-induced charging technique
J.RUAN, D.TREMOUILLES, F.COCCETTI, N.NOLHIER, G.J.PAPAIOANNOU, R.PLANA
MINC, ISGE, Athenes
Revue Scientifique : Journal of Micromechanics and Microengineering, Vol.22, N°4, 045016p., Avril 2012 , N° 12246
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127232An accelerated stress test method for electrostatically driven MEMS devices
J.RUAN, N.MONNEREAU, D.TREMOUILLES, N.MAURAN, F.COCCETTI, N.NOLHIER, R.PLANA
MINC, ISGE, 2I
Revue Scientifique : IEEE Transactions on Instrumentation and Measurement, pp.456-461, Février 2012, DOI : 10.1109/TIM.2011.2161937 , N° 12049
Lien : http://hal.archives-ouvertes.fr/hal-00668827
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Abstract
This paper addresses an innovative solution to develop a circuit to perform accelerated stress tests of capacitive microelectromechanical-system (MEMS) switches and shows the use of instruments and equipment to monitor physical aging phenomena. A dedicated test circuit was designed and fabricated in order to meet the need for accelerated techniques for those structures. It integrated an in-house miniaturized circuit connected to additional test equipment (e.g., oscilloscopes and capacitance meters) that enabled the reliability characterization of capacitive switches. The accelerated stress test (AST) circuit generated an electrostatic-discharge-like impulse that stressed the device. This setup allowed the simultaneous measurement of the current and voltage waveforms, and the capacitance variation of the device under test after each stress. The results obtained using the miniature AST circuit were discussed and were correlated with results obtained using a commercial human-body-model tester as well as data from a cycling benchmark. The scope of this paper encompasses the theory, methodology, and practice of measurement; the development of a testing miniaturized board; and the analysis and representation of the information obtained from a set of measurements. As a result, it may contribute to the scientific and technical standards in the field of instrumentation and measurement of electrostactically actuated devices having insulating layers.
Behavioral-modeling methodology to predict electrostatic-discharge susceptibility failures at system level: an IBIS improvement
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Manifestation avec acte : EMC Europe 2011, York (UK), 26-30 Septembre 2011, pp.457-463 , N° 11069
Lien : http://hal.archives-ouvertes.fr/hal-00722643
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Abstract
In this paper, a behavioral modeling methodology to predict ElectroStatic-Discharge (ESD) failures at system level is proposed and validated. The proposed models enable time domain simulation to determine voltage and current waveforms inside and outside an IC during ESD events in order to predict the susceptibility of an electronic system to ESD. Very-high-speed integrated circuit Hardware Description Language - Analog and Mixed Signals (VHDL-AMS) is used as the description language. The purpose of this methodology is based on the improvement of Input Output Buffer Information Specification (IBIS) models widely used in signal integrity (SI) simulation. In this paper the additional information required to be added to IBIS files is described, and comparison between simulations and measurements are exposed.
Compte rendu intermédiaire T0+18
K.ABOUDA, M.BAFLEUR, P.BESSE, F.CAIGNET, F.LAFON, J.P.LAINE, N.NOLHIER, N.MONNEREAU, S.RIGOUR, A.SALLES, D.TREMOUILLES, A.WANG
FREESCALE, ISGE, Valeo
Rapport de Contrat : Projet ANR-09-VTT-07-01, Septembre 2011, 8p. , N° 11479
Non diffusable
125281Investingating the probability of susceptibility failure within ESD system level consideration
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Manifestation avec acte : Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD 2011), Anaheim (USA), 11-16 Septembre 2011, pp.6A.2-1-6A.2-6 , N° 11058
Diffusable
Plus d'informations
Abstract
Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.