234documents trouvés
Technologie des circuits intégrés de puissance
M.BAFLEUR, P.RAGUET
ISGE, EXT
Ouvrage (contribution) : Physique et modélisation des composants et des circuits intégrés de puissance, Chapitre 5, Hermes, 2007, pp.3-78 , N° 07711
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112488Optimizing pulsed OBIC technique for ESD defect localization
F.ESSELY, N.GUITARD, F.DARRACQ, V.POUGET, M.BAFLEUR, P.PERDU, A.D.TOUBOUL, D.LEWIS
IXL, ISGE, CNES-THALES
Revue Scientifique : IEEE Transactions on Device and Materials Reliability, Vol.7, N°4, pp.617-624, Décembre 2007 , N° 06088
Lien : http://hal.archives-ouvertes.fr/hal-00382949/fr/
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Abstract
The evolution of laser sources has led to the advent of new laser-based techniques for failure analysis. The pulsed OBIC (optical beam induced current) technique is one of them, which is based on the photoelectric laser stimulation of the device under test (DUT) at a micrometric scale. The suitability of this technique to localize failure sites resulting from electrostatic discharges (ESD) has previously been demonstrated. This paper presents a complementary work on the OBIC experimental procedure for defect localization improving the sensitivity of this technique and thus the probability to localize very small size defects
Electrostatic discharge failure analysis of capacitive RF MEMS switches
J.RUAN, N.NOLHIER, M.BAFLEUR, L.BARY, F.COCCETTI, T.LISEC, R.PLANA
MINC, ISGE, 2I, FHG
Revue Scientifique : Microelectronics Reliability, Vol.47, N°9-11, pp.1818-1822, Novembre 2007 , N° 07676
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This paper reports on the investigation of failure mechanisms of AlN-based capacitive RF MEMS switches. Electrostatic Discharge (ESD) experiments have been carried out by means of a Transmission Line Pulsing (TLP) technique. It has been observed that ESD stresses create some electric arcs and the degradations have been observed and analyzed. Microwave measurements have shown that ESD stress impacts the quality of the capacitive contact.
Long-term reliability of silicon bipolar transistors subjected to low constraints
A.CROSSON, L.ESCOTTE, M.BAFLEUR, D.TALBOURDET, L.CRETINON, P.PERDU, G.PEREZ
MOST, ISGE, EDF, CNES-THALES, CNES
Manifestation avec acte : 18th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Arcachon (France), 8-12 Octobre 2007, pp.1590-1594 , N° 07209
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We present in this study the effect of electrical ageing on silicon (Si) NPN bipolar transistors. This study is based on a sample of halfhundred components, which have been fabricated in the early 1980s, which represents an exceptional experience feedback. By means of static and low frequency noise measurements, which are used as diagnostic tools for reliability assessment, we have noticed a good accordance with a physical model based on an oxide charge modulation. We have also used emission microscopy and electron beam-induced current analysis in order to visualize and to localize the defects in the structure. These have been located in the spacer oxide at the periphery of the base-emitter junction.
Identification of the physical signature of CDM induced latent defects into a DC-DC converter using low frequency noise measurement
Y.GAO, N.GUITARD, C.SALAMERO, M.BAFLEUR, L.ESCOTTE, P.GUEULLE, L.LESCOUZERES
ISGE, MOST, ON Semiconductor
Manifestation avec acte : 18th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Arcachon (France), 8-12 Octobre 2007, pp.1456-1461 , N° 07166
Lien : http://hal.archives-ouvertes.fr/hal-00385697/fr/
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In this paper, it is demonstrated that low frequency noise measurements are an efficient tool for the detection of latent defects induced by CDM stress in a complex circuit such as a DCDC converter. This technique is able to detect the presence of a defect whereas classical electrical testing techniques such as Iddq or functionality test fail. In addition, a correlation between the noise signature and the nature of the defect is established. In particular, the presence of trapped charges in the oxides is clearly identified.
Electrostatic discharge failure analysis of capacitive RF MEMS switches
J.RUAN, N.NOLHIER, M.BAFLEUR, L.BARY, F.COCCETTI, T.LISEC, R.PLANA
MINC, ISGE, 2I, FHG
Manifestation avec acte : 18th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Arcachon (France), 8-12 Octobre 2007, pp.1818-1822 , N° 07676
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Abstract
This paper reports on the investigation of failure mechanisms of AlN-based capacitive RF MEMS switches. Electrostatic Discharge (ESD) experiments have been carried out by means of a Transmission Line Pulsing (TLP) technique. It has been observed that ESD stresses create some electric arcs and the degradations have been observed and analyzed. Microwave measurements have shown that ESD stress impacts the quality of the capacitive contact.
SEB characterisation of commercial power MOSFETs with backside laser and heavy ions of different ranges
A.LUU, F.MILLER, P.POIROT, P.AUSTIN, R.GAILLARD, N. BUARD, T.CARRIERE, M.BAFLEUR, G.SARRABAYROUSE
EADS, INFODUC SARL, ISGE, M2D
Manifestation avec acte : 9th European Conference Radiation and Its Effects on Components and Systems (RADECS 2007), Deauville (France), 10-14 Septembre 2007, 5p. , N° 07514
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This paper presents a validation of the methodology based upon backside laser irradiations to characterize the sensitivity of power devices towards Single-Event Burnout. This is done thanks to high-energy heavy ion testing and device simulations.
Mots-Clés / Keywords
Commercial power MOSFETs; SEB; Laser tests; Heavy ion tests; Software simulations;
Characterization and modeling methodology for IC's ESD susceptibility at system level using VF-TLP tester
N.LACRAMPE, F.CAIGNET, N.NOLHIER, M.BAFLEUR
ISGE
Manifestation avec acte : 29th Electrical Overstress/Electrostatic Discharge Symposium, Anaheim (USA), 16-21 Septembre 2007, 7p. , N° 07015
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This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A Very Fast Transmission Line Pulsing (VF-TLP) tester is used to inject a disturbance into an IC under operation. A system failure criterion is chosen and a critical stress level is extracted. A modeling methodology is also developed to precisely describe each part of the set up and provide a complete model that describes the IC response to ESD indirect effects.
High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology
P.RENAUD, A.GENDRON, M.BAFLEUR, N.NOLHIER
FREESCALE, FREESCALE USA, ISGE
Manifestation avec acte : IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2007), Boston (USA), 30 Septembre - 2 Octobre 2007, pp.226-229 , N° 07677
Lien : http://hal.archives-ouvertes.fr/hal-00195362/fr/
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A new device dedicated to the ESD protection of high voltage I/Os is presented. In addition to the use of specific design guidelines, the concept consists in coupling an open-base lateral PNP with a vertical avalanche diode within the same structure to obtain a non-snapback behavior together with very good RON capabilities (~1©). The protection of high voltage I/Os with a narrow ESD design window ranging from 80V to 100V can be implemented in a reduced surface of 151*140 ¼m2, which represents a state-of-the-art breakthrough.
Mots-Clés / Keywords
ESD protection; High voltage I/Os; Smart power technology; PNP bipolar transistor;
Investigation on ESD transient immunity of integrated circuits
N.LACRAMPE, A.ALAELDINE, F.CAIGNET, R.PERDRIAU, M.BAFLEUR, N.NOLHIER, M.RAMDANI
ISGE, ESEO
Manifestation avec acte : 2007 IEEE International Symposium on Electromagnetic Compatibility, Honolulu (USA), 8-13 Juillet 2007 , N° 06824
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Abstract
This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a Very Fast Transmission Line Pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full custom 0.18 ¼m CMOS IC.