208documents trouvés
Robustesse des logiciels exécutifs : caractérisation de l'impact de pilotes défaillants par injection de fautes
A.ALBINET, J.ARLAT, J.C.FABRE
TSF
Revue Scientifique : Technique et Science Informatiques, Vol.27, N°9-10, pp.1253-1286, Octobre 2008 , N° 06640
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Mots-Clés / Keywords
Système d'exploitation; Noyau; Logiciel pilote; Evaluation expérimentale; Injection de fautes; Caractérisation des modes de défaillance;
Benchmarking the impact of faulty drivers: Application to the linux kernel
A.ALBINET, J.ARLAT, J.C.FABRE
TSF
Ouvrage (contribution) : Dependability Benchmarking for Computer Systems, N°ISBN 978-0-470-23055-8, 2008, Chapitre 14, pp.285-310 , N° 06351
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115573Safety and security architectures for avionics
Y.LAAROUCHI, Y.DESWARTE, D.POWELL, J.ARLAT
TSF
Manifestation avec acte : Doctoral Consortium (DCSOFT 2008) of the 3rd International Conference on Software and Data Technologies (ICSOFT 2008), Porto (Portugal), 5-8 Juillet 2008, 5p. , N° 08290
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Mots-Clés / Keywords
Critical systems; Integrity levels; Virtualization; Information flow validation;
Fault tolerance of the Input/Output ports in massively defective multicore processor chips
P.ZAJAC, J.H.COLLET, J.ARLAT, Y.CROUZET
TSF
Manifestation avec acte : 2nd Workshop on Dependable & Secure Nanocomputing, Anchorage (USA), 27 Juin 2008, 5p. , N° 08188
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Abstract
This paper addresses the fault tolerance issues concerning the input-output ports (IOPs) of future multicore chips built up using massively defective nanotechnologies. Recall that the IOPs are critical to system dependability as they constitute bottlenecks for all communications between the chip and external resources. Various levels of modular redundancy in the IOPs are being considered for which we calculate the probability to maintain correct operation. We also calculate the cost attached to the proposed protective designs for the IOP, in terms of circuitry overhead.
Mots-Clés / Keywords
Ultra-large-scale integration; Nanotechnology; Multicore processor architecture; Fault tolerance;
Evaluation methodologies, techniques and tools (final version). Deliverable n° D4.1.2
P.LOLLINI, A.BONDAVALLI, J.ARLAT, M.CLEMETSEN, L.FALAI, A.F.HANSEN, M.B.HANSEN, M.KAANICHE, K.KANOUN, M.KOVACS, Y.LIU, M.MAGYAR, I.MAJZIK, E.V.MATTHIESEN, A.NICKELSEN, J.J.NIELSEN, J.G.RASMUSSEN, T.RENIER, H.P.SCHWEFEL
UNIFI, TSF, TELENOR, AAU, BME Hungary, AAU Danemark
Rapport de Contrat : HIDENETS, Project IST-FP6-STREP-26979, Janvier 2008, 112p. , N° 08031
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112769Nanoscale technologies: prospect or hazard to dependable and secure computing ?
J.ARLAT
TSF
Manifestation avec acte : 3rd Latin-American Symposium on Dependable Computing, Morelia (Mexique), 26-28 Septembre 2007, pp.3-6 , N° 07350
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Abstract
The continuous advances and progress made in hardware technologies makes it possible to foresee a realm of unprecedented performance levels and of new application-driven architectural designs, e. g., see [1]. One of the main drivers is the reduction of the size of the elementary devices. Nevertheless, the evolution of nanoscale technologies raises serious challenges with respect to both dependability and security viewpoints. Issues at stake encompass three main types of concerns i) unreliability and variability that will characterize the production of emerging nanoscale devices, ii) accidental disturbances that affect the operation of the systems, iii) malicious threats targeting vulnerabilities of hardware circuits. However, on the other hand, thanks to the large scale integration, one may expect the fault tolerance techniques to come to the rescue of the limitations of the currently dominating fault avoidance approaches. After a brief review of each of these issues, we will provide a few hints concerning a proposal for resilient multicore processor chips.
Revised reference model. Deliverable n° D1.2
J.ARLAT, M.KAANICHE, A.BONDAVALLI, M.CALHA, A.CASIMIRO, A.DAIDONE, L.FALAI, G.HUSZERL, M.O.KILLIJIAN, A.KOVI, Y.LIU, P.LOLLINI, E.V.MATTHIESEN, M.RADIMIRSCH, T.RENIER, N.RIVIERE, M.ROY, H.P.SCHWEFEL, I.E.SVINNSET, H.WAESELYNCK
TSF, UNIFI, FCUL Portugal, BME Hungary, AAU, AAU Danemark, Carmeq, TELENOR
Rapport de Contrat : HIDENETS, Project IST-FP6-STREP-26979, Août 2007, 86p. , N° 07456
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111259Resilience through self-configuration in the future massively defective nanochips
P.ZAJAC, J.H.COLLET, J.ARLAT, Y.CROUZET
TSF
Manifestation avec acte : 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2007), Edimbourg (UK), 25-28 Juin 2007, pp.266-271 , N° 07154
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110571Workshop on dependable and secure nanocomputing
J.ARLAT, R.IYER, M.NICOLAIDIS
TSF, Urbana, TIMA/CNRS
Manifestation avec acte : 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2007), Edimbourg (UK), 25-28 Juin 2007, pp.809-810 , N° 07167
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110570A high integrity error checking scheme for communication networks in critical control systems
A.YOUSSEF, J.ARLAT, Y.CROUZET, A.DE BONNEVAL, J.J.AUBERT, P.BROT
TSF, AIRBUS France
Rapport LAAS N°07306, Mars 2007, 30p.
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