Retour au site du LAAS-CNRS

Abstract

Nowadays, the "On-Resistance" reduction is key factor in the evolution of power devices, especially in power MOSFETs technology. In that way, innovating structures such as SuperJunction (SJ) [1] or Floating Islands (FI) [2, 3, 4] devices have been developed. Previously, a Vertical N-channel FLYMOSFET, including one level of P buried layers called Floating Islands (introduced in the N-epitaxial region), has been successfully developed [5, 6]. In this paper, new design and process improvements provide for the first time a FLYMOSFET with two levels of FI exhibiting a low specific on-resistance (RON.S) of 4.5m¿.cm2 in 200V breakdown voltage (BVdss) range which breaks the silicon limit [7]. Furthermore, a full physical and electrical characterization is presented, especially in dynamic configuration to evaluate FLYMOSFET's performances. Then a manufactured 200V SJ product from another company is analyzed and compared to it. FLYMOSFET appears as a good alternative to 200V SJ devices.

Abstract

In this paper, a new SPICE-compatible circuit model for low-voltage power FLIMOSFETs is presented. This modeling is based on device physics and uses a new expression for the currentvoltage characteristics in the linear region. Consequently, the new model gives better results than the SPICE level 3 MOS model, widely used for power MOSFET models. In addition, the interelectrode capacitances are taken into account in the model. Finally, the new model is validated by comparing the simulated and measured static and dynamic characteristics.

Mots-Clés / Keywords

SPICE-compatible model; Power VDMOSFET; FLIMOSFET; Validation;

Abstract

A vertical N-channel 150-200 V FLYMOSFET concept has been applied on silicon: its P-buried layer introduced in the N2 epitaxial region, called "P floating island", is the key factor for superior performance. A particular physical characterisation technique, scanning capacitance microscopy, is used on a power device to establish 2D and 3D island representation and to go beyond 1D information given by spreading resistance profiling. Experiments including four different boron implantations of P floating islands and two different spacings of the basic cell are conducted, because the form and the concentration of the floating islands and, moreover, the spacing between them directly impact the electrical performance. Concerning the electrical study, FLYMOSFET measurements show good "specific on-resistance/breakdown voltage" (RON.S- BVdss) trade-offs, better than the conventional VDMOSFETs, and UIS ruggedness as good as superjunction MOSFETs.

Mots-Clés / Keywords

Power MOSFET; Floating Islands; FLYMOS; Superjunction; Breakdown voltage; Specific On-resistance; Spreding resistance profiling (SRP); Scanning capacitance microscopy (SCM); 2D/3D physical characterization;

Abstract

Thin film SOI is a key technology for wireless and RF applications. We demonstrate the successful transfer of a DriftMOS transistor from the 130 nm technology to the 65 nm one on thin SOI. The process option introduced in this node enables to achieve high device performance: due to the new well patterning strategy, the main transistor figure of merit is improved.

Mots-Clés / Keywords

Power semiconductor devices; MOSFET; Super junction devices; Traction application;

Abstract

New hybrid vehicles will probably use high voltage batteries (150 to 200 Volts). For these future automotive applications, the development of 600 Volts power MOSFET switches exhibiting low on-resistance is desired. The "Deep Trench SuperJunction" MOSFET (DT-SJMOSFET) is one of the new candidates. In this paper, a comparative theoretical study, using 2D simulations, shows that the DT-SJMOSFET should be a challenger to the conventional SJMOSFET in terms of "specific on-resistance / breakdown voltage" trade-off. Simulations of the DT-SJMOSFET breakdown voltage versus the technological parameters exhibit the difficulties to fabricate the device. Finally, an original edge cell is proposed that contains the peripheral potential.

Mots-Clés / Keywords

Power semiconductor devices; MOSFET; SuperJunction devices; Simulation;

Abstract

In this paper, a new SPICE-compatible circuit model for low voltage, low on-resistance power FLYMOSFETs is presented for the first time. In this new structure, the improvement of the on-resistance has been obtained by inserting floating islands in the lowly doped layer. Our modelling is based on device physics, analytical study and on experimental characterization. The inter-electrode capacitances are modelled accurately as nonlinear functions, and good agreement between simulation and measurements is found.

Abstract

The use of super-junction (SJ) techniques in PIN photodiodes is proposed in this letter for the first time with the objective to assist the optoelectronic integrated circuits (OEICs) implementation in complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS) and bipolar-CMOS-double diffused MOS (BCD) technologies. Its technological viability is also discussed to make it credible as an alternative to other OEICs approaches. Numerical simulation of realistic SJ-PIN devices, widely used in high power electronics, demonstrates the possibility to integrate high-performance CMOS-based OEICs in epitaxial layers with doping concentrations above 1×1015 cm-3. The induced lateral depletion at low reverse biased voltage, assisted by the alternated N and P-doped pillars, allows high-speed transient response in SJ-PIN detecting wavelengths between 400 and 800 nm. Moreover, other important parameters as the responsivity and the dark current are not degraded in respect to the conventional PIN (C-PIN) structures.

Mots-Clés / Keywords

Optoelectronic devices; Superjunction; Charge compensation; Photodiodes; OEIC; CMOS integrated circuits;