7documents trouvés
Estimating the attraction domain for the boost inverter
C.ALBEA SANCHEZ, F.GORDILLO
SARA, Seville
Revue Scientifique : Vol.15, N°1, pp.169-176, Janvier 2013 , N° 12039
Lien : http://hal.archives-ouvertes.fr/hal-00750720
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Abstract
This work presents an approach for estimating the domain of attraction for polynomial systems with state and control-signal constraints including saturation. In many problems, it is possible to derive global stability properties for such systems, neglecting constraints. Consideration of the constraints usually makes the problem much more involved. In this paper, the stability analysis performed for the unconstrained case is used for the problem as a whole. For application of the method, there are powerful computational tools that can be employed in cases of polynomial systems. The technique is not only valid for the analysis of equilibrium points but also for other attractors, such as limit cycles. As examples, the domain of attraction for given control laws is estimated for a nonlinear DC-DC boost converter as well as for a boost inverter.
Controlled QoS guarantee in communication network
C.ALBEA SANCHEZ, F.GOUAISBAUT, Y.LABIT
MAC, SARA
Rapport LAAS N°12683, Décembre 2012, 12p.
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128773Advanced coupled voltage-frequency control for power efficient DVFS management
C.ALBEA SANCHEZ, D.PUSCHINI, S.LESECQ, Y.AKGUL
SARA, CEA/LETI/MINATEC
Manifestation avec acte : Annual Conference of the IEEE Industrial Electronics Society ( IECON ) 2012 du 25 octobre au 28 novembre 2012, Montréal (Canada), 2012, 10p. , N° 12201
Lien : http://hal.archives-ouvertes.fr/hal-00763136
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Abstract
Power management is a hot-topic in complex System-on-Chip (SoC) designs. In the context of advanced technologies, Dynamic Voltage-Frequency Scaling (DVFS) techniques are widely proposed to improve e ciency. Nowadays, these mechanisms are composed of independent actuators controlling the applied voltage and clock frequency. A prede ned sequence has to be used to switch from one state to another in order to avoid timing faults but increasing the energy cost. The timing of the sequence depends on the dynamic response of actuators. In this work, an external controller is designed in order to couple both actuators to manage the voltage and frequency transient periods, increasing power e ciency The proposed controller has been implemented to couple a Vdd-hopping mechanism with a Frequency-Lock Loop circuit.
High performance control for a frequency-locked loop
C.ALBEA SANCHEZ, D.PUSCHINI, S.LESECQ
SARA, CEA/LETI/MINATEC
Rapport LAAS N°12293, Juin 2012, 8p.
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127411Robust saturated control for low-power circuits
C.ALBEA SANCHEZ, F.GORDILLO, C.CANUDAS DE WIT
SARA, Seville, GIPSA-Lab
Rapport LAAS N°12077, DOI 10.1109/TCST.2012.2185237, Mars 2012, 19p.
Lien : http://hal.archives-ouvertes.fr/hal-00256631
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Abstract
An important issue in the trends of miniaturization of Systems on Chips (SoCs) is to obtain a high energy efficiency. This can be reached by Dynamic Voltage Scaling (DVS) architectures as the noveldiscrete Vdd-Hopping circuit. Generally, this kind of systems present parameter uncertainties and delays. Likewise, current peaks and energy dissipation must be reduced. In this paper, an optimal and robust saturated control law is proposed for this Vdd-Hopping circuit via Lyapunov-Krasovskii theory that ensures asymptotic stability as well as system robustness with respect to delay presence and parameter uncertainties. The closed-loop system presents a regional stabilization due to the actuator saturation. An estimation of an attraction domain is provided. This controller also limites the current peaks and it provides an energy-aware performance. The advantages achieved with this controller are shown in simulation.
Optimal and robust saturated control for a clock generator
C.ALBEA SANCHEZ, S.LESECQ, D.PUSCHINI
OLC, CEA/LETI/MINATEC
Manifestation avec acte : IEEE Conference on Decision and Control and European Control Conference (CDC-ECC 2011), Orlando (USA), 12-15 Décembre 2011, pp.657-662 , N° 11539
Lien : http://hal.archives-ouvertes.fr/hal-00256628
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Abstract
Fine-grain Dynamic Voltage and Fre- quency Scaling (DVFS) is becoming a requirement for Globally-Asynchronous Locally-Synchronous (GALS) architectures. However, the area overhead of adding voltage and frequency control engines in each volt- age/frequency island must be taken into account to optimize the circuit. This paper focuses on the control for the frequency actuator. An optimal and robust saturated control law, with a minimum hardware implementation area is proposed for a Clock Gen- erator, taking into account the delay introduced by the sensor. This controller is designed with Lyapunov-Krasovskii theory that ensures asymptotic stability, disturbance rejection as well as system robustness with respect to delay presence and parameter uncertainties. The closed-loop system presents a regional stabilization due to the actuator saturation. An estimation of a maximum attraction domain is provided. The performance achieved with this controller are shown in simulation.
Control robusto y optimo de una FLL en nanocircuitos
C.ALBEA SANCHEZ, D.PUSCHINI, S.LESECQ, E.BEIGNE
OLC, CEA/LETI/MINATEC
Manifestation avec acte : Jornadas de Automatica (JA 2011), Séville (Espagne), 7-9 Septembre 2011, 8p. , N° 11426
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