11documents trouvés
Enhancing accuracy of low-dropout regulator susceptibility extraction with on-chip sensors
J.F.WU, E.SICARD, A.BOYER, S.BEN DHIA, J.LI , R.SHEN
NUDT, INSAT, ISGE
Revue Scientifique : Electronics Letters, Vol.48, N°11, pp.649-650, Mai 2012 , N° 12305
Lien : http://hal.archives-ouvertes.fr/hal-00709287
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Presented is a new test method that consists in monitoring on-chip internal voltages during susceptibility tests of integrated circuits. An on-chip sensor was installed at several internal nodes within low dropout regulators to measure the distortion of internal signals induced by the coupling of electromagnetic interference. The comparison between external and internal measurement results shows that on-chip sensor techniques enhance the extraction of circuit susceptibility levels, especially at high frequencies.
On-chip noise sensor for integrated circuit susceptibility investigations
S.BEN DHIA, A.BOYER, B.VRIGNON, M.DEOBARRO, T.V.DINH
ISGE, FREESCALE, LATTIS, Toulouse
Revue Scientifique : IEEE Transactions on Instrumentation and Measurement, Vol.61, N°3, pp.696-707, Mars 2012 , N° 12047
Lien : http://hal.archives-ouvertes.fr/hal-00668627
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With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins.
A new approach to modeling the impact of EMI on MOSFET DC behavior
R.FERNANDEZ GARCIA, I.GIL, A.BOYER, S.BEN DHIA, B.VRIGNON
UPC, ISGE, FREESCALE
Revue Scientifique : IEICE Transactions on Electronics, Vol.E94-C, N°12, pp.1906-1908, Décembre 2011 , N° 11796
Lien : http://hal.archives-ouvertes.fr/hal-00669506
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A simple analytical model to predict the DC MOSFET behaviour under electromagnetic interference (EMI) is presented. The model is able to describe the MOSFET performance in linear and saturation regime under EMI disturbance applied on the gate. The model consists of a unique simple equivalent circuit based on a voltage dependant current source and a reduced number of parameters which can accurately predict the drift on the drain current due to the EMI source. The analytical approach has been validated by means of electric simulation and measurements and can be easily introduced in circuit simulators. The proposed modelling technique combined with the nth-power law model of the MOSFET without EMI, significantly improves its accuracy in comparison with the nth-power law directly applied to a MOSFET under EMI impact.
An alternative approach to model the Internal Activity of integrated circuits
N.BERBEL, R.FERNANDEZ GARCIA, I.GIL, B.LI, S.BEN DHIA, A.BOYER
UPC, ISGE
Manifestation avec acte : International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2011), Dubrovnik (Croatie), 6-9 Novembre 2011, 5p. , N° 11799
Lien : http://hal.archives-ouvertes.fr/hal-00669719
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This paper deals with the EMC modeling of integrated circuits and the standardized model IEC 62433-2 (Integrated Circuit Emission Model - Conducted Emission [1]). This standardized model has been applied into a basic digital circuit: a ring oscillator. This work presents an alternative approach to model and quantify the Internal Activity of any digital or analog integrated circuit, and its use has been applied on the ring oscillator.
Construction and evaluation of the susceptibility odel of an integrated phase-locked loop
A.BOYER, S.BEN DHIA, C. LEMOINE, B.VRIGNON
ISGE, LATTIS, Toulouse, FREESCALE
Manifestation avec acte : International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2011), Dubrovnik (Croatie), 6-9 Novembre 2011, 6p. , N° 11800
Lien : http://hal.archives-ouvertes.fr/hal-00669716
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Developing integrated circuit immunity models has become one of the major concerns of integrated circuits suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign process. This paper presents the development process of the susceptibility model an integrated phase-locked loop to harmonic disturbances up to 1 GHz. The model construction is based on basic circuit information and S parameter measurements. An evaluation of the model accuracy is ensured by the characterization of internal voltage fluctuations with an on-chip sensor.
Enhancing engineers skills in EMC of integrated circuits
E.SICARD, A.BOYER
INSAT, ISGE
Manifestation avec acte : International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2011), Dubrovnik (Croatie), 6-9 Novembre 2011, 4p. , N° 11798
Lien : http://hal.archives-ouvertes.fr/hal-00669721
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This paper presents the strategies used for effective training of engineers in integrated circuit (IC) design under Electromagnetic Compatibility (EMC) constraints. It presents the general context of EMC of ICs and details the EMC-aware IC design course given in companies and several institutes in France. Collaborations with industry have produced a set of learning resources and design tools to support the development of industry relevant EMC skills and lifelong learning skills. The courses enable students to learn about EMC measurements and modeling at IC level and their implications using a set of user friendly tools. The courses taught in university and in industry have consistently produced high levels of student/engineer satisfaction.
An on-chip sensor for time domain characterization of electromagnetic interferences
A.BOYER, S.BEN DHIA, C. LEMOINE, B.VRIGNON
ISGE, LATTIS, Toulouse, FREESCALE
Manifestation avec acte : International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2011), Dubrovnik (Croatie), 6-9 Novembre 2011, 6p. , N° 11801
Lien : http://hal.archives-ouvertes.fr/hal-00669533
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With the growing concerns about susceptibility of integrated circuits to electromagnetic interferences, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation. This paper presents an on-chip noise sensor dedicated to the time-domain measurement of voltage fluctuations induced by interference coupling.
Study of the impact of hot carrier injection to immunity of MOSFET to electromagnetic interferences
B.LI, N.BERBEL, A.BOYER, S.BEN DHIA, R.FERNANDEZ GARCIA
ISGE, UPC
Manifestation avec acte : European Symposium Reliability of Electron Devices Failure Physics and Analysis (ESREF 2011), Bordeaux (France), 3-7 Octobre 2011, 5p. , N° 11797
Lien : http://hal.archives-ouvertes.fr/hal-00669726
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This paper presents an original study about the effect of hot carrier injection stress on the DC offsets induced by electromagnetic interferences (EMI) on a nanometric NMOS transistor, which is one of the major sources of failures in analog circuits. Measurements and simulations based on a simple model (Sakurai-Newton model) of fresh and stressed transistors are presented showing significant variations of EMI-induced DC shifts of drain current.
Experimental verification of the usefulness of the nth power law MOSFET model under hot carrier wearout
N.BERBEL, R.FERNANDEZ GARCIA, I.GIL, B.LI, A.BOYER, S.BEN DHIA
UPC, ISGE
Revue Scientifique : Microelectronics Reliability, Vol.51, N°9, pp.1564-1567, Septembre 2011 , N° 11821
Lien : http://hal.archives-ouvertes.fr/hal-00669511
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In this paper the usefulness of the nth power law MOSFET model under Hot Carrier Injection (HCI) wearout has been experimentally demonstrated. In order to do that, three types of nFET transistors have been analyzed under different HCI conditions and the nth power law MOSFET model has been extracted for each sample. The results show that the model can reproduce the MOSFET behavior under HCI wearout mechanism. Therefore, the impact of HCI on circuits can be analyzed by using the nth power law MOSFET model.
Ageing effect on electromagnetic susceptibility of a phase locked loop
B.LI, A.BOYER, S.BEN DHIA, C. LEMOINE
ISGE, LATTIS, Toulouse
Revue Scientifique : Microelectronics Reliability, Vol.50, N°9-11, pp.1304-1308, Septembre 2010 , N° 10958
Lien : http://hal.archives-ouvertes.fr/hal-00669515
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Phase locked loop in radiofrequency and mixed signal integrated circuit experience noise as electromagnetic interference coupled on input and power supply which translates to the timing jitter. Most of PLL noise analysis did not take into account the ageing effect. However device ageing can degrade the physical parameters of transistors and makes noise impact worse. This paper deals with the analyses of PLL immunity drift after accelerated ageing.