67documents trouvés
Size effects on varistor properties made from zinc oxide nanoparticles by low temperature spark plasma sintering
L.SAINT-MACARY, M.L.KAHN, C.ESTOURNES, P.FAU, D.TREMOUILLES, M.BAFLEUR, P.RENAUD, B.CHAUDRET
LCC, CIRIMAT, ISGE, FREESCALE
Revue Scientifique : Advanced Functional Materials, Vol.19, N°11, pp.1775-1783, Mai 2009 , N° 08428
Lien : http://hal.archives-ouvertes.fr/hal-00383348/fr/
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Abstract
Conditions for the elaboration of nanostructured varistors by Spark Plasma Sintering (SPS) are investigated, using 8 nm zinc oxide nanoparticles synthesized following an organometallic approach. A binary system constituted of zinc oxide and bismuth oxides nanoparticles is used for this purpose. It is synthesized at room temperature in an organic solution through the hydrolysis of dicyclohexylzinc and bismuth acetate precursors. Sintering of this material is performed by SPS at various temperatures and dwell times. The determination of the microstructure and the chemical composition of the as prepared ceramics are based on Scanning Electron Microscopy (SEM) and X-Ray Diffraction (XRD) analysis. The non linear electrical characteristics are evidenced by current-voltage (I-V) measurements. The breakdown voltage of these nanostructured varistors strongly depends on grain sizes. The results show for the first time that, nanostructured varistors are obtained by SPS at sintering temperatures ranging from 550 to 600°C.
Mots-Clés / Keywords
Organometallic; Zinc oxide; Nanoparticles; Spark plasma sintering; Varistor;
La fiabilité d'un MEMS-RF capacitif en bande W soumis à des décharges électrostatiques
J.RUAN, N.NOLHIER, G.J.PAPAIOANNOU, D.TREMOUILLES, F.COCCETTI, R.PLANA
MINC, ISGE, Athenes, 2I
Manifestation avec acte : 16èmes Journées Nationales Microondes (JNM 2009), Grenoble (France), 27-29 Mai 2009, 4p. , N° 09246
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117675Characterization and optimization of sub-32nm FinFET devices ESD applications
S.THIJS, D.TREMOUILLES, C.RUSS, A.GRIFFONI, N.COLLAERT, R.ROOYACKERS, D.LINTEN, M.SCHOLZ, C.DUVVURY, H.GOSSNER, M.JURCZAK, G.GROESENEKEN
IMEC, ISGE, INFINEON, Texas Instruments
Revue Scientifique : IEEE Transactions on Electron Devices, Vol.55, N°12, pp.3507-3516, Décembre 2008 , N° 08401
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Electrostatic discharge performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing parameters. Both N- and P-type MOS FinFET devices are characterized in bipolar operation mode as a function of layout parameters such as gate length and fin width. The impact of well implants, selective epitaxial growth, and strain is studied.
Mots-Clés / Keywords
Electrostatic discharge (ESD); FinFET; Multiplegate FET (MuGFET); Silicon on Insulator (SOI); Transmission Line Pulse; Human Body Model;
Pushing away the silicon limits of ESD protection structures: exploration of crystallographic orientation
D.TREMOUILLES, Y.GAO, M.BAFLEUR
ISGE
Manifestation avec acte : BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), Monterey (USA), 13-15 Octobre 2008, pp.200-203 , N° 08378
Lien : http://hal.archives-ouvertes.fr/hal-00383353/fr/
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Improving the ESD robustness of integrated protection structures to cope with the constraints of severe environments such as the automotive one is a real challenge. Getting a deep understanding of the involved high injection physics during an ESD stress helps defining specific design guidelines. The grounded-base NPN bipolar transistor is a popular and efficient protection device. In this paper, we explore the impact of crystal orientation on the electrical characteristics and the robustness of this device. It is shown for the first time that orienting the structure 45° with respect to the wafer flat allows significantly improving its on-resistance. A 30% improvement is measured on the device under study.
Mots-Clés / Keywords
Grounded-base bipolar transistor; Electrostatic discharge (ESD); Impact ionisation; ESD protection; Crystal orientation;
Design methodology of FinFET devices that meet IC-level HBM ESD targets
S.THIJS, C.RUSS, D.TREMOUILLES, A.GRIFFONI, D.LINTEN, M.SCHOLZ, N.COLLAERT, R.ROOYACKERS, M.JURCZAK, M.SAWADA, T.NAKAEI, T.HASEBE, C.DUVVURY, H.GOSSNER, G.GROESENEKEN
IMEC, INFINEON, ISGE, Hanwa, Texas Instruments
Manifestation avec acte : Electrical Overstress/Electrostatic Discharge Symposium (EOS-ESD), Tucson (USA), 7-12 Septembre 2008, pp.295-303 , N° 08402
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115650Impact of strain on ESD robustness of FinFET devices
A.GRIFFONI, S.THIJS, C.RUSS, D.TREMOUILLES, M.SCHOLZ, D.LINTEN, N.COLLAERT, R.ROOYACKERS, C.DUVVURY, H.GOSSNER, G.MENEGHESSO, G.GROESENEKEN
IMEC, INFINEON, ISGE, Texas Instruments, University of Padova
Manifestation avec acte : IEEE International Electron Devices Meeting (IEDM 2008), San Francisco (USA), 15-17 Janvier 2008, 5p. , N° 08399
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The ESD performance of multi-gate NMOS devices is investigated in both active MOS-diode and parasiticbipolar mode, highlighting the impact of strained SiN layers. Strain improves the ESD robustness up to 30 % in multi-fin FinFETs. A different failure mechanism is discovered in strained devices.
Improving ESD robustness through guard ring efficiency assessment and optimization. A novel methodology
D.TREMOUILLES, M.SCHOLZ, M.I.NATARAJAN, M.BAFLEUR, M.SAWADA, T.HASEBE, G.GROESENEKEN
IMEC, ISGE, Hanwa
Manifestation avec acte : 45th annual IEEE international Reliability Physics symposium, 2007 , Phoenix (USA), 15-19 Avril 2007, pp.606-607 , N° 06202
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The new measurement methodology allows extracting guard ring efficiency under ESD stress conditions. A new figure of merit to design latch-up protection around ESD protection structures is defined and showed that an optimal sizing of critical dimension can be achieved to enhanced ESD protection levels. The efficiency of the approach opens a new area to study latch-up guard ring design with respect to ESD stress conditions. The methodology could be used to address the impact of technology parameters like STI depth, doping profiles and is generic enough to be applied to any kind of ESD protection strategies and devices
Different failure signatures of multiple TLP and HBM stresses in an ESD robust protection structure
N.GUITARD, D.TREMOUILLES, P.PERDU, D.LEWIS, V.POUGET, F.ESSELY, M.BAFLEUR, N.NOLHIER, A.TOUBOUL
CIP, CNES-THALES, IXL
Revue Scientifique : Microelectronics Reliability, Vol.45, N°9-11, pp.1415-1420, Septembre-Novembre 2005 , N° 05220
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104831Different failure signatures of multiple TLP and HBM stresses in an ESD robust protection structure
N.GUITARD, D.TREMOUILLES, P.PERDU, D.LEWIS, V.POUGET, F.ESSELY, M.BAFLEUR, N.NOLHIER, A.TOUBOUL
CIP, CNES-THALES, IXL
Manifestation avec acte : 16th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'2005), Arcachon (France), 10-14 Octobre 2005 , N° 05220
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104830Low frequency noise measurements for ESD latent defect detection in high reliability applications
N.GUITARD, D.TREMOUILLES, M.BAFLEUR, L.ESCOTTE, L.BARY, P.PERDU, G.SARRABAYROUSE, N.NOLHIER, R.REYNA ROJAS
CIP, CISHT, 2I, CNES-THALES, TMN, CNES
Manifestation avec acte : 15th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'2004), Zurich (Suisse), 4-8 Octobre 2004 , N° 04284
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