67documents trouvés
Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD Propagation
N.MONNEREAU, F.CAIGNET, D.TREMOUILLES, N.NOLHIER, M.BAFLEUR
ISGE, ESE
Papier invité dans une revue : Microelectronics Reliability, 8p., Décembre 2012, http://dx.doi.org/10.1016/j.microrel.2012.04.012 , N° 10099
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128684Investingating the probability of susceptibility failure within ESD system level consideration
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Revue Scientifique : IEEE Transactions on Device and Materials Reliability, Vol.12, N°4, pp.599-606, Décembre 2012, DOI 10.1109/TDMR.2012.2218605 , N° 11058
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Abstract
Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.
Reliability assessment of electrostatically driven MEMS devices: based on a pulse-induced charging technique
J.RUAN, D.TREMOUILLES, F.COCCETTI, N.NOLHIER, G.J.PAPAIOANNOU, R.PLANA
MINC, ISGE, Athenes
Revue Scientifique : Journal of Micromechanics and Microengineering, Vol.22, N°4, 045016p., Avril 2012 , N° 12246
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127232An accelerated stress test method for electrostatically driven MEMS devices
J.RUAN, N.MONNEREAU, D.TREMOUILLES, N.MAURAN, F.COCCETTI, N.NOLHIER, R.PLANA
MINC, ISGE, 2I
Revue Scientifique : IEEE Transactions on Instrumentation and Measurement, pp.456-461, Février 2012, DOI : 10.1109/TIM.2011.2161937 , N° 12049
Lien : http://hal.archives-ouvertes.fr/hal-00668827
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Abstract
This paper addresses an innovative solution to develop a circuit to perform accelerated stress tests of capacitive microelectromechanical-system (MEMS) switches and shows the use of instruments and equipment to monitor physical aging phenomena. A dedicated test circuit was designed and fabricated in order to meet the need for accelerated techniques for those structures. It integrated an in-house miniaturized circuit connected to additional test equipment (e.g., oscilloscopes and capacitance meters) that enabled the reliability characterization of capacitive switches. The accelerated stress test (AST) circuit generated an electrostatic-discharge-like impulse that stressed the device. This setup allowed the simultaneous measurement of the current and voltage waveforms, and the capacitance variation of the device under test after each stress. The results obtained using the miniature AST circuit were discussed and were correlated with results obtained using a commercial human-body-model tester as well as data from a cycling benchmark. The scope of this paper encompasses the theory, methodology, and practice of measurement; the development of a testing miniaturized board; and the analysis and representation of the information obtained from a set of measurements. As a result, it may contribute to the scientific and technical standards in the field of instrumentation and measurement of electrostactically actuated devices having insulating layers.
Understanding the failure mechanisms of protection diodes during system level ESD: toward repetitive stresses robustness
M.DIATTA, D.TREMOUILLES, E.BOUYSSOU, R.PERDREAU, C.ANCEAU, M.BAFLEUR
ISGE, ST
Revue Scientifique : IEEE Transactions on Electron Devices, Vol.59, N°1, pp.108-113, Janvier 2012 , N° 12048
Lien : http://hal.archives-ouvertes.fr/hal-00668818
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Abstract
In electronic systems, the ever-increasing level of integration is paced by component scaling. Consequently, system-level protection improvements in electrostatic discharge (ESD) reliability during a device's lifetime are mandatory. To this end, we have investigated bidirectional system-level ESD protection diodes that have been subjected to repetitive human metal model stresses. Our goal was to develop robust ESD components by understanding the physical and electrical behaviors of components after multiple ESD surges. In this paper, three ESD-induced failure modes of protection devices are demonstrated and analyzed in terms of severity, i.e., charge trapping in the silicon-oxide interface, metallic diffusion toward the contacts, and melted filaments in the silicon bulk at the junction periphery.
Behavioral-modeling methodology to predict electrostatic-discharge susceptibility failures at system level: an IBIS improvement
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Manifestation avec acte : EMC Europe 2011, York (UK), 26-30 Septembre 2011, pp.457-463 , N° 11069
Lien : http://hal.archives-ouvertes.fr/hal-00722643
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Abstract
In this paper, a behavioral modeling methodology to predict ElectroStatic-Discharge (ESD) failures at system level is proposed and validated. The proposed models enable time domain simulation to determine voltage and current waveforms inside and outside an IC during ESD events in order to predict the susceptibility of an electronic system to ESD. Very-high-speed integrated circuit Hardware Description Language - Analog and Mixed Signals (VHDL-AMS) is used as the description language. The purpose of this methodology is based on the improvement of Input Output Buffer Information Specification (IBIS) models widely used in signal integrity (SI) simulation. In this paper the additional information required to be added to IBIS files is described, and comparison between simulations and measurements are exposed.
Compte rendu intermédiaire T0+18
K.ABOUDA, M.BAFLEUR, P.BESSE, F.CAIGNET, F.LAFON, J.P.LAINE, N.NOLHIER, N.MONNEREAU, S.RIGOUR, A.SALLES, D.TREMOUILLES, A.WANG
FREESCALE, ISGE, Valeo
Rapport de Contrat : Projet ANR-09-VTT-07-01, Septembre 2011, 8p. , N° 11479
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125281ESD system level characterization and modeling methods applied to a LIN transceiver
P.BESSE, F.LAFON, N.MONNEREAU, F.CAIGNET, J.P.LAINE, A.SALLES, S.RIGOUR, M.BAFLEUR, N.NOLHIER, D.TREMOUILLES
FREESCALE, Valeo, ISGE
Manifestation avec acte : Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD 2011), Anaheim (USA), 11-16 Septembre 2011, pp.5B.3-1-5B.3-9 , N° 11059
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125587Investingating the probability of susceptibility failure within ESD system level consideration
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Manifestation avec acte : Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD 2011), Anaheim (USA), 11-16 Septembre 2011, pp.6A.2-1-6A.2-6 , N° 11058
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Abstract
Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.
High temperature operation MOS-IGBT power clamps for improved EDS protection in smart power SOI technology
H.ARBESS, D.TREMOUILLES, M.BAFLEUR
ISGE
Manifestation avec acte : Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD 2011), Anaheim (USA), 11-16 Septembre 2011, pp.1B.2-1-1B.2-8 , N° 11087
Lien : http://hal.archives-ouvertes.fr/hal-00722642
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Abstract
We propose a new MOS-IGBT power clamp for high-temperature operation providing a very compact high-robustness ESD protection with low temperature sensitivity. It is achieved by inserting in the same LDMOS device P+ diffusions in the drain with various N+/P+ ratios whose impact on RON and holding current at high temperatures is thoroughly studied.