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Abstract

This paper introduces a new bipolar differential pair topology for both Gaussian and sinusoidal signal shaping, to be used as a phase-to-amplitude converter alternative in low-power ultra-high-speed DDS. A DDS using this converter, with a 9-bit frequency resolution and an 8-bit amplitude resolution has been designed in a 0.13 μm SiGe BiCMOS technology, with ft/fmax of 200/250 GHz, and simulated up to a 20 GHz operating clock frequency. It consumes 585 mW under a 2.8 V power supply. Simulated triangle shape allows an optimal SFDR of -44.5 dBc in sinus mode and a SLRR of -43.5 dBc in Gaussian mode.

Abstract

This paper presents a novel architecture of a low spurious level fractional-N frequency divider. It has already been shown in previous work that the use of a direct digital synthesizer (DDS) represents a promising solution to the mitigation of the fractional spurs that appear at the output of fractional frequency dividers, but with the drawback of causing a non-linear control of the division ratio. The DDS-based architecture proposed in this paper recovers the benefit of having a linear tuning of the division ratio, while still having similar performance in terms of fractional spurs.

Abstract

Un étage différentiel capable de mettre en forme des signaux gaussiens aussi bien que sinusoïdaux est proposé comme alternative dans les architectures de DDS basse consommation ultra rapides. Il a permis la conception d'un DDS fonctionnant jusqu'à 20GHz, avec une résolution de 9bits en fréquence et de 8bits en amplitude, sur une technologie SiGe BiCMOS 0,13µm de ft/fmax égal à 200/250GHz. Il conduit à un SFDR de −44,5dBc en mode sinusoïdal et un SLRR de −43,5dBc en mode gaussien.

Abstract

The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and onchip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 ¼m design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This operational amplifier provides both low noise and high gain performances. This operational amplifier has an area of only 660×250 ¼m2 with an equivalent input noise floor of only 1.1 nV/Hz square root at 10 kHz. The measured noise characteristics (versus total power consumption) are better than those of most operational amplifiers commonly adopted in low-frequency noise measurements. The AC gain is 83 dB and the unity gain bandwidth is 210 MHz, with a total current consumption of 18 mA at 2.5 V supply voltage.

Abstract

A low phase noise and wide-bandwidth frequency divider has been developed in a 0.25 ¼m SiGe:C process. This paper discusses the BiCMOS design improvements used for ultra low phase noise applications like on-chip phase-noise measurement circuit. From a singleended signal provided by a local oscillator LO, the widebandwidth frequency divider circuit generates accurate quadrature signals. For the full 1kHz-5.5 GHz input frequency range, the frequency divider achieves an output quadrature error less than ±1°. This paper presents a novel architecture designed for improving phase noise and exhibits a measured residual phase noise of -164 dBc/Hz @ 100 kHz with a 3.5 GHz input frequency.

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