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Résumé

La réalisation des transistors MOS de taille "ultime" nécessite la fabrication de jonctions source et drain ultra-minces (quelques dizaines de nanomètres), abruptes et fortement dopées. L'optimisation du procédé de fabrication de ces jonctions nécessite la compréhension des phénomènes physiques qui interviennent lors des différentes étapes de fabrication, en particulier l'impact des défauts cristallins sur leurs paramètres électriques. Dans ce travail, nous avons étudié l'impact des précipités de bore (BICs, Boron-Interstitial Clusters) mais aussi des défauts EOR (End-Of-Range), sur la mobilité des porteurs et l'activation des dopants (principalement le bore dans le silicium). Tout d'abord, nous avons développé un modèle d'analyse mathématique basé sur le profil de concentration des dopants mesuré par SIMS et sur les valeurs " standards " de mobilité des porteurs. Ce modèle permet de déterminer par le calcul les trois paramètres électriques mesurés par effet Hall : la résistance carrée, la dose active de dopants et la mobilité des porteurs. A partir de l'utilisation de ce modèle, nous démontrons qu'en présence de BICs, il s'avère nécessaire de modifier la valeur d'un facteur correctif, le facteur de scattering, essentiel pour les mesures par effet Hall, et nous déterminons sa valeur. Nous mettons ensuite en évidence la dégradation de la mobilité des porteurs par les BICs, puis étudions de manière plus quantitative l'évolution de cette dégradation en fonction de la quantité de BICs. Par la suite, une étude sur l'activation du bore en présence de défauts EOR est menée. Enfin, nous élargissons notre étude sur ces mêmes paramètres électriques au cas de nouveaux matériaux tels que le SOI (Silicon-On-Insulator) ou le SiGe (alliage silicium/germanium), matériaux utilisés pour les dernières générations de transistors.

Abstract

To continue the scaling down of CMOS devices, high doped ultra-shallow source/drain junctions must be fabricated. The optimization of the fabrication process of these junctions needs the understanding of the physical phenomena occurring during the various fabrication steps, particularly the crystalline defects' impact on their electrical parameters. In this work, we investigated the impact of Boron-Interstitial Clusters (BICs) and End-Of-Range (EOR) defects on dopant carrier mobility and activation (mainly boron in silicon). Firstly, we developed an analysis model based on the dopant concentration profile measured by SIMS and "standard" values of carrier mobilities. This model allows to determine the three electrical parameters measured by Hall effect: sheet resistance, dopant active dose and carrier mobility. Thanks to this model, we demonstrate that in presence of BICs, the Hall scattering factor, a corrective factor essential for Hall effect measurements, is modified and we determine its new value. Next, we highlight the carrier mobility degradation by the BICs, and we study it more quantitatively as a function of BICs concentration. Then, a study of boron activation in presence of EOR defects is done. Finally, we considered the case of new materials, such as Silicon-On-Insulator (SOI) and silicon/germanium alloys (Si1-xGex), currently used for the latest transistors generations.

Mots-Clés / Keywords

Jonctions ultra minces; Implantation ionique; Défauts cristallins; BICs; EOR; Bore; Effet Hall; Facteur de scattering; Mobilité des porteurs; Dose active; SIMS; Silicium sur isolant; Alliage SiGe; Ultra-shallow junctions; Ion implantation; Crystalline defects; Hall effect; Hall scattering factor; Carrier mobility; Active dose; Silicon on Insulator (SOI); Silicon/Germanium;

Abstract

Millisecond annealing as an equipment technology provides temperature profiles which favour dopant activation but nearly eliminate dopant diffusion to form extremely shallow, highly electrically activated junctions. For the 45-nm technology node and beyond, precisely controlled gate under-diffusion is required for optimum device performance. Therefore, on boron and arsenic beamline-implanted wafers, various annealing schemes were investigated for the formation of ultra-shallow and custom-shaped junctions. The main scheme consisted of flash annealing with peak temperatures ranging from 1250 to 1300 °C, combined with spike rapid thermal annealing with peak temperatures in the range from 900 to 1000 °C to achieve a desired junction depth. As alternative, to reduce the sheet resistance of pMOS and nMOS source-drain extensions, combinations of two or three flash anneals in succession were tested. Finally, the standard flash anneal condition of a 750 °C intermediate temperature followed by the flash anneal was changed to a high intermediate temperature of 950 °C followed by the flash anneal up to 1300 °C. The results of all these annealing schemes were analysed by four-point probe measurement. Selected samples were analysed by Hall-effect measurements for peak activation, and by secondary ion mass spectrometry for profile shape as well as diffusion effects. Transmission electron microscopy was used to study residual defects. Selected boron and arsenic dopant profiles were also compared to predictive simulation results which address the diffusion and activation at extrinsic concentrations.

Abstract

Current fabrication processes of MOS source/drain ultra-shallow junctions (dopant implantation in a preamorphised substrate, followed by ultra-rapid anneals at high temperature) generate defects which can degrade their electrical properties. The understanding of the physical phenomena responsible for this degradation is essential for the optimization of the fabrication processes. Among these phenomena, the impact of Boron Interstitial Clusters (BICs) on the carrier mobility has not yet been clearly understood. In this work, we present an empirical method for the self-consistent interpretation of SIMS and Hall effect measurements of boron doped ultra-shallow junctions that allows to estimate the activation level of the doped layers (maximum active dopant concentration, active dose fraction) and, for the case of partially activated structures, to assess whether or not the carrier mobility is affected by the electrically inactive BICs. Both epitaxial and implanted structures were studied. We found that, depending on the fabrication conditions, the maximum active dopant concentrations extracted from the studied samples may differ from the boron solid solubility at the process temperature. In addition, for the partially electrically active structures, a degradation of the drift mobility due to the presence of BICs is shown, which is experimentally confirmed by low temperature Hall effect measurements, indicating the existence of an additional Coulomb-type scattering mechanism.

Mots-Clés / Keywords

Ultra shallow junctions; Hole mobility; Hall effect; Boron interstitial clusters; SIMS;

Abstract

The pile-up of arsenic at the Si/SiO2 interface after As implantation and annealing was investigated by high resolution Z-contrast imaging, electron energy-loss spectroscopy (EELS), grazing incidence x-ray fluorescence spectroscopy (GI-XRF), secondary ion mass spectrometry, x-ray photoelectron spectroscopy, Rutherford backscattering spectrometry, as well as Hall mobility and four-point probe resistivity measurements. After properly taking into account their respective artifacts, the results of all methods are compatible with each other, with EELS and GI-XRF combined with etching providing similar spatial resolution on the nanometer scale for the dopant profile. The sheet concentration of the piled-up As at the interface was found to be ~1×1015 cm2 for an implanted dose of 1×1016 cm2 with a maximum concentration of ~10 at. %. The strain observed in the Z-contrast images also suggests a significant concentration of local distortions within 3 nm from the interface, which, however, do not seem to involve intrinsic point defects.

Abstract

The segregation and pile-up of arsenic atoms at the Si/SiO2 interface in steady state was investigated in detail by a combination of gracing incidence x-ray fluorescence spectroscopy (GI-XRF) measurements, electrical measurements, etching on the nanometer scale, and measurements of the step heights by interferometry. Using GI-XRF measurements and removal of the highly doped segregation layer by a sensitive etching process it was possible to distinguish clearly between the piled-up atoms and the arsenic atoms in the bulk over a large range of implantation doses, from 3×1012 to 1×1016 cm2. The samples were annealed at different temperatures from 900 °C to 1200 °C for time periods long enough to make sure that the segregation reflects an equilibrium state. With additional step height measurements at line-space structures, the thickness of the layer with the piled-up arsenic and the shape of the segregation profile was determined. Electrical measurements indicated that the segregated arsenic atoms are deep donors with an electrical activity that increases eventually to full electrical activation for high sheet concentrations of the segregated atoms. The measured data can be modeled as a steady state of neutral arsenic atoms in the segregation layer with positively charged substitutional arsenic atoms and free electrons. For the highest concentration, a saturation of the sheet concentration of segregated arsenic atoms was observed that correlates with the increase in electrical activation. For the use in process simulation programs, a three-phase segregation model was adapted and calibrated.

Mots-Clés / Keywords

Arsenic; Silicon; Surface segregation; TXRF; GI-XRF;

Abstract

Current fabrication processes of MOS source/drain ultra-shallow junctions (dopant implantation in a preamorphised substrate, followed by ultra-rapid anneals at high temperature) generate defects which can degrade their electrical properties. The understanding of the physical phenomena responsible for this degradation is essential for the optimization of the fabrication processes. Among these phenomena, the impact of Boron Interstitial Clusters (BICs) on the carrier mobility has not yet been clearly understood. In this work, we present an empirical method for the self-consistent interpretation of SIMS and Hall effect measurements of boron doped ultra-shallow junctions that allows to estimate the activation level of the doped layers (maximum active dopant concentration, active dose fraction) and, for the case of partially activated structures, to assess whether or not the carrier mobility is affected by the electrically inactive BICs. Both epitaxial and implanted structures were studied. We found that, depending on the fabrication conditions, the maximum active dopant concentrations extracted from the studied samples may differ from the boron solid solubility at the process temperature. In addition, for the partially electrically active structures, a degradation of the drift mobility due to the presence of BICs is shown, which is experimentally confirmed by low temperature Hall effect measurements, indicating the existence of an additional Coulomb-type scattering mechanism.

Mots-Clés / Keywords

Ultra shallow junctions; Hole mobility; Hall effect; Boron interstitial clusters; SIMS;

Abstract

Millisecond annealing as an equipment technology provides temperature profiles which favour dopant activation but nearly eliminate dopant diffusion to form extremely shallow, highly electrically activated junctions. For the 45-nm technology node and beyond, precisely controlled gate under-diffusion is required for optimum device performance. Therefore, on boron and arsenic beamline-implanted wafers, various annealing schemes were investigated for the formation of ultra-shallow and custom-shaped junctions. The main scheme consisted of flash annealing with peak temperatures ranging from 1250 to 1300 °C, combined with spike rapid thermal annealing with peak temperatures in the range from 900 to 1000 °C to achieve a desired junction depth. As alternative, to reduce the sheet resistance of pMOS and nMOS source-drain extensions, combinations of two or three flash anneals in succession were tested. Finally, the standard flash anneal condition of a 750 °C intermediate temperature followed by the flash anneal was changed to a high intermediate temperature of 950 °C followed by the flash anneal up to 1300 °C. The results of all these annealing schemes were analysed by four-point probe measurement. Selected samples were analysed by Hall-effect measurements for peak activation, and by secondary ion mass spectrometry for profile shape as well as diffusion effects. Transmission electron microscopy was used to study residual defects. Selected boron and arsenic dopant profiles were also compared to predictive simulation results which address the diffusion and activation at extrinsic concentrations.