32documents trouvés
Compte-rendu intermédiaire T0+6
M.BAFLEUR, F.CAIGNET, K.ABOUDA, P.BESSE, F.LAFON, J.P.LAINE, N.MONNEREAU, N.NOLHIER, A.SALLES, S.RIGOUR, D.TREMOUILLES, A.WANG
ISGE, FREESCALE, Valeo
Rapport de Contrat : Projet ANR-09-VTT-07-01, Septembre 2010, 5p. , N° 10532
Non diffusable
122453Impact of a decoupling capacitance on ESD propagation at system Level : Simulation an d Measurement Comparison
N.MONNEREAU, F.CAIGNET, D.TREMOUILLES
ISGE
Manifestation sans acte : ANADEF (12ème atelier), Port d'Albret (France), 1-4 Juin 2010, 1p. , N° 10033
Diffusable
123614Non-invasive system level ESD current measurement using magnetic field probe
F.CAIGNET, N.MONNEREAU, N.NOLHIER
ISGE
Manifestation avec acte : International Electrostatic Discharge Workshop 2010, Tutzing (Allemagne), 10-13 Mai 2010, 17p. , N° 10435
Diffusable
122323Impact of a decoupling capacitance on ESD propagation at system Level : Simulation an d Measurement Comparison
N.MONNEREAU, F.CAIGNET, D.TREMOUILLES
ISGE
Manifestation avec acte : International Electrostatic Discharge Workshop 2010, Tutzing (Allemagne), 10-13 Mai 2010, 23p. , N° 10033
Diffusable
122321Simple ICs-internal-protection models for system level ESD simulation
D.TREMOUILLES, N.MONNEREAU, F.CAIGNET, M.BAFLEUR
ISGE
Manifestation avec acte : International Electrostatic Discharge Workshop 2010, Tutzing (Allemagne), 10-13 Mai 2010, 23p. , N° 10034
Diffusable
122322Mesures et modélisation des protections contre les décharges électrostatiques d'un circuit intégré: application à l'extraction de modèle de protection du composant 74LVC04A
N.MONNEREAU, D.TREMOUILLES, F.CAIGNET
ISGE
Rapport LAAS N°09418, Juillet 2009, 43p.
Non diffusable
118355Rapport final du laboratoire commun LISPA
P.ALOISI, C.ALONSO, M.BAFLEUR, V.BOITIER, F.CAIGNET, P.DUBREUIL, B.ESTIBALS, E.IMBERNON, K.ISOIRD, H.E.DKOTB MAHFOZ, N.MAURAN, F.MORANCHO, N.NOLHIER, J.ROIG GUITART, B.ROUSSET, C.SALAMERO, J.L.SANCHEZ, E.SCHEID, H.TRANDUC, B.CHAUDRET, M.KHAN, A.MAISONNAT, C.ESTOURNES, J.L.CHAPTAL, A.DERAM, R.ESCOFFIER, U.MONIRAT, P.RENAUD, J.M.REYNES, J.SHEPHERD, E.STEFANOV, B.VRIGNON, L.CALVENTE, L.MARTINEZ, E.VIDAL, P.ARTILLAN, B.BERNOUX, A.GENDRON, N.LACRAMPE, L.SAINT-MACARY, J.B.SAUVEPLANE, A.SIMON
ISGE, TEAM, 2I, M2D, LCC, CIRIMAT, FREESCALE, TARRAGONE, FREESCALE USA
Rapport de Contrat : Laboraoire commun LISPA, Octobre 2008, 40p. , N° 08526
Non diffusable
115245Investigation of effects of an ESD pulse injected by a near-field probe into an oscillator block of a 16-bit microcontroller
B.VRIGNON, N.LACRAMPE, F.CAIGNET
FREESCALE, ISGE
Manifestation avec acte : 6th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2007), Torino (Italie), 28-30 Novembre 2007, 6p. , N° 07557
Diffusable
113032Characterization and modeling methodology for IC's ESD susceptibility at system level using VF-TLP tester
N.LACRAMPE, F.CAIGNET, N.NOLHIER, M.BAFLEUR
ISGE
Manifestation avec acte : 29th Electrical Overstress/Electrostatic Discharge Symposium, Anaheim (USA), 16-21 Septembre 2007, 7p. , N° 07015
Diffusable
Plus d'informations
Abstract
This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A Very Fast Transmission Line Pulsing (VF-TLP) tester is used to inject a disturbance into an IC under operation. A system failure criterion is chosen and a critical stress level is extracted. A modeling methodology is also developed to precisely describe each part of the set up and provide a complete model that describes the IC response to ESD indirect effects.
Investigation on ESD transient immunity of integrated circuits
N.LACRAMPE, A.ALAELDINE, F.CAIGNET, R.PERDRIAU, M.BAFLEUR, N.NOLHIER, M.RAMDANI
ISGE, ESEO
Manifestation avec acte : 2007 IEEE International Symposium on Electromagnetic Compatibility, Honolulu (USA), 8-13 Juillet 2007 , N° 06824
Diffusable
Plus d'informations
Abstract
This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a Very Fast Transmission Line Pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full custom 0.18 ¼m CMOS IC.