32documents trouvés
Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD Propagation
N.MONNEREAU, F.CAIGNET, D.TREMOUILLES, N.NOLHIER, M.BAFLEUR
ISGE, ESE
Papier invité dans une revue : Microelectronics Reliability, 8p., Décembre 2012, http://dx.doi.org/10.1016/j.microrel.2012.04.012 , N° 10099
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128684Investingating the probability of susceptibility failure within ESD system level consideration
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Revue Scientifique : IEEE Transactions on Device and Materials Reliability, Vol.12, N°4, pp.599-606, Décembre 2012, DOI 10.1109/TDMR.2012.2218605 , N° 11058
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Abstract
Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.
Behavioral ESD protection modeling to perform system level ESD efficient design
F.CAIGNET, N.MONNEREAU, N.NOLHIER, M.BAFLEUR
ISGE, ESE
Conférence invitée : Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC 2012), Singapour (Singapour), 21-24 Mai 2012, pp.401-404 , N° 12442
Lien : http://hal.archives-ouvertes.fr/hal-00722644
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Abstract
For both Equipment Manufacturers (EM) and semiconductor suppliers, the prediction of ElectroStatic Discharge (ESD) events into design phase is becoming a challenging issue to insure rehability into system level considerations. This is mainly due to the shrinking of Integrated Circuits (IC) technology, which decreases the robustness level and increase the probability of failures. In this paper, we will present how to build IC's models taking into account behavioral description of ESD protections, to perform system level ESD simulations. The IBIS (Input/output Buffer Information Specification) models are mixed with information extracted from Transmission Line Pulsing (TLP) measurement's techniques to build system simulations. The methodology is detailed and proved in some case studies addressing the current propagation path and the susceptibility of the ICs. The main goal of the proposed model is that it could be shared by IC suppliers and EMs to ensure that ICs can handle system level ESD events.
Behavioral-modeling methodology to predict electrostatic-discharge susceptibility failures at system level: an IBIS improvement
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Manifestation avec acte : EMC Europe 2011, York (UK), 26-30 Septembre 2011, pp.457-463 , N° 11069
Lien : http://hal.archives-ouvertes.fr/hal-00722643
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Abstract
In this paper, a behavioral modeling methodology to predict ElectroStatic-Discharge (ESD) failures at system level is proposed and validated. The proposed models enable time domain simulation to determine voltage and current waveforms inside and outside an IC during ESD events in order to predict the susceptibility of an electronic system to ESD. Very-high-speed integrated circuit Hardware Description Language - Analog and Mixed Signals (VHDL-AMS) is used as the description language. The purpose of this methodology is based on the improvement of Input Output Buffer Information Specification (IBIS) models widely used in signal integrity (SI) simulation. In this paper the additional information required to be added to IBIS files is described, and comparison between simulations and measurements are exposed.
Compte rendu intermédiaire T0+18
K.ABOUDA, M.BAFLEUR, P.BESSE, F.CAIGNET, F.LAFON, J.P.LAINE, N.NOLHIER, N.MONNEREAU, S.RIGOUR, A.SALLES, D.TREMOUILLES, A.WANG
FREESCALE, ISGE, Valeo
Rapport de Contrat : Projet ANR-09-VTT-07-01, Septembre 2011, 8p. , N° 11479
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125281ESD system level characterization and modeling methods applied to a LIN transceiver
P.BESSE, F.LAFON, N.MONNEREAU, F.CAIGNET, J.P.LAINE, A.SALLES, S.RIGOUR, M.BAFLEUR, N.NOLHIER, D.TREMOUILLES
FREESCALE, Valeo, ISGE
Manifestation avec acte : Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD 2011), Anaheim (USA), 11-16 Septembre 2011, pp.5B.3-1-5B.3-9 , N° 11059
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125587Investingating the probability of susceptibility failure within ESD system level consideration
N.MONNEREAU, F.CAIGNET, N.NOLHIER, D.TREMOUILLES, M.BAFLEUR
ISGE
Manifestation avec acte : Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD 2011), Anaheim (USA), 11-16 Septembre 2011, pp.6A.2-1-6A.2-6 , N° 11058
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Plus d'informations
Abstract
Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.
Very high bandwith ESD on-chip sampling measurement waveform in system level conditions
F.CAIGNET, A.WANG, N.MAURAN, N.MONNEREAU, N.NOLHIER
ISGE, 2I
Rapport LAAS N°11060, Février 2011, 4p.
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123995Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD Propagation
N.MONNEREAU, F.CAIGNET, D.TREMOUILLES, N.NOLHIER, M.BAFLEUR
ISGE, ESE
Manifestation avec acte : Electrical Overstress / Electrostatic Discharge Symposium (EOS/ESD Symposium 2010), Reno (USA), 3-8 Octobre 2010, pp.127-136 , N° 10099
Diffusable
122827Pressure wireless micro-sensor distribution on a sail for dynamic measurement
F.CAIGNET
ISGE
Rapport LAAS N°10623, Octobre 2010, 3p.
Diffusion restreinte
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