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Abstract

Current fabrication processes of MOS source/drain ultra-shallow junctions (dopant implantation in a preamorphised substrate, followed by ultra-rapid anneals at high temperature) generate defects which can degrade their electrical properties. The understanding of the physical phenomena responsible for this degradation is essential for the optimization of the fabrication processes. Among these phenomena, the impact of Boron Interstitial Clusters (BICs) on the carrier mobility has not yet been clearly understood. In this work, we present an empirical method for the self-consistent interpretation of SIMS and Hall effect measurements of boron doped ultra-shallow junctions that allows to estimate the activation level of the doped layers (maximum active dopant concentration, active dose fraction) and, for the case of partially activated structures, to assess whether or not the carrier mobility is affected by the electrically inactive BICs. Both epitaxial and implanted structures were studied. We found that, depending on the fabrication conditions, the maximum active dopant concentrations extracted from the studied samples may differ from the boron solid solubility at the process temperature. In addition, for the partially electrically active structures, a degradation of the drift mobility due to the presence of BICs is shown, which is experimentally confirmed by low temperature Hall effect measurements, indicating the existence of an additional Coulomb-type scattering mechanism.

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Abstract

The effects of surface proximity and B concentration on end-of-range defect formation during nonmelt laser annealing in preamorphized silicon have been studied. These effects were analyzed by observing the activation and diffusion of an ultrashallow B implant, using Hall effect and secondary ion mass spectrometry measurements. By adjusting the preamorphizing implant and laser annealing conditions, B deactivation and diffusion were minimized, resulting in a sheet resistance of ~600 /sq with a 16 nm junction depth. This is attributed to a combination of enhanced dissolution of end-of-range defects and preferential formation of B-interstitial clusters due to the surface proximity and high B concentration, respectively.

Abstract

Based on electrical measurements and transmission electron microscopy (TEM) imaging, we propose an explanation for the electron and hole mobility degradation with gate length reduction in metaloxidesemiconductor field effect transistors (MOSFETs). We demonstrate that ion implantation, normally used for source/drain doping, is responsible for transport degradation for short-channel devices. Implantation impact on electrons and holes mobility was investigated both on silicon-on-insulator (SOI) and tensile strained silicon-on-insulator (sSOI) substrates. Wafers with ultrathin Si films (from 8 to 35 nm) were Ge implanted at 3 keV and various concentrations (from 5×1014 to 2×1015 atoms cm2), then annealed at 600 °C for 1 h. Secondary ion mass spectrometry enabled us to quantify the Ge-implanted atoms concentrations. The end-of-range defects impact on mobility was investigated with the pseudo-MOSFET technique. Measurements showed a mobility decrease as the implantation dose increased. We demonstrated that sSOI mobility is more sensitive to implantation than SOI mobility, without any implantation-induced strain relaxation in sSOI (checked using the ultraviolet Raman technique). A 36% (25%) holes (electrons) mobility degradation was measured for sSOI, while SOI presented a 21% mobility degradation for holes and 5% for electrons. Finally, the electrical results were compared with morphological studies. Plan-view TEM showed the presence of interstitial defects formed during ion implantation and annealing. The defect density was estimated to be two times higher in sSOI than in SOI, which is in full agreement with electrical results mentioned before. The results are relevant for the optimization of the source and drain regions of advanced nanoscale SOI and sSOI transistors.

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Abstract

In this paper, we investigate the evolution of extended defects during a millisecond Flash anneal after a preamorphising implant. The experimental results, supported by predictive simulations, indicate that during the ultra-fast temperature ramp-up and rump-down occurring in a millisecond Flash anneal, the basic mechanisms that control the growth and evolution of extended defects are not modified with respect to the relatively slower annealing processes, such as "soak" and "spike" Rapid Thermal Annealing. In addition, we have observed a decrease in the number of trapped interstitials in the End-Of-Range (EOR) defects when decreasing the Ge+ amorphisation energy from 30 keV down to 2 keV. This result is ascribed to two concomitant phenomena: (i) the increase of the initial number of interstitials, Ni, created by the amorphisation step, when the implant energy is decreased and (ii) the efficient interstitial annihilation at the silicon surface, whose recombination length, Lsurf, is in the nanometer range even at the very high temperatures employed in millisecond Flash anneals.

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Abstract

Experimental data obtained in bulk and silicon on insulator (SOI) structures by transmission electron microscopy (TEM) are reported showing that the density of extended defects in SOI structures is reduced in comparison with bulk silicon. Additional data obtained on strained SOI structures show that a less pronounced reduction is observed in these structures. It will also be shown that simulations based on an already existing model and taking into account the effect of the Si/BOX interface acting as a sink for interstitials are not able to explain the experimentally observed defect density reduction in unstrained SOI.

Abstract

Different shallow n-type and p-type dopants were annealed with spike, flash, and a combination of spike+flash or vice versa to find the optimum annealing condition for both activation and diffusion. The implant conditions investigated during this study were 74Ge+ with 11B+ as well as 11B+, 49BF2+, and 75As+. The wafers were characterized regarding sheet resistance, junction depth, and chemical dose. An electrically active dose was derived from the Hall-effect measurement. Transmission electron microscopy analysis for the characterization of defects was done on selected samples. Boron implanted into crystalline as well as preamorphized silicon shows a similarly low sheet resistance which is independent of whether they are annealed with spike+flash, flash, or flash+spike. For arsenic by far the lowest sheet resistance is seen with a combination of spike+flash anneal. The main advantage when using a spike+flash anneal combination is that similar sheet resistance values for arsenic and boron implant can be achieved with the same anneal sequence.